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Two quadrant analogue squarer circuit based on MOS square-law characteristic

Two quadrant analogue squarer circuit based on MOS square-law characteristic

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© The Institution of Electrical Engineers
Published

A novel analogue CMOS circuit is presented which performs the arithmetical squaring of a voltage, using the square-law characteristic of the MOS transistor in saturation. The core circuit is constructed from four identical building blocks, which are connected so as to eliminate all unwanted offset terms. Simulation results from HSPICE are presented where the circuit is used for doubling the frequency of a sinusoidal input.

Inspec keywords: CMOS integrated circuits; linear integrated circuits; analogue computer circuits

Other keywords: sinusoid frequency doubling; MOS transistor in saturation; arithmetical squaring; analogue CMOS circuit; HSPICE; quadrant analogue squarer circuit; four identical building blocks; eliminate all unwanted offset terms; squaring of voltage signal; MOS square-law characteristic

Subjects: Analogue processing circuits; CMOS integrated circuits; Analogue circuits

References

    1. 1)
      • J. Pena-Finol , J.A. Connelly . A MOS four-quadrant analog multiplier using the quarter-square technique. IEEE J. Solid-State Circuits , 1064 - 1073
    2. 2)
      • Z. Wang , W. Guggenbühl . A voltage-controllable MOS transconductor using bias offset technique. IEEE J. Solid-State Circuits , 315 - 317
    3. 3)
      • K. Bult , H. Wallinga . A class of analog CMOS circuits based on the square law characteristic of an MOS transistor in saturation. IEEE J. Solid-State Circuits , 357 - 365
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