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GaAs Vertical pin diode using MeV implantation

GaAs Vertical pin diode using MeV implantation

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Vertical pin diodes were fabricated using MeV Si/S coimplantation and keV Be/P coimplantation into undoped semi-insulating GaAs to obtain buried n+ and surface p+ regions, respectively. An exploratory device with a 500 × 500 μm2 junction area and a 3 μm thick intrinsic region had a break-down voltage of 70 V, reverse leakage current density of 40 μA/cm2 at 20 V, an off-state capacitance of 3.9nF/cm2 and a DC forward resistance of 2.4 Ω at 100 mA.

References

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      • Seymour, D.J., Heston, D.D., Lehmann, R.E., Zych, D.: `X-band monolithic GaAs PIN diode variable attenuation limiter', IEEE MTT-S Dig., 1990, p. 841–844.
    2. 2)
      • P.E. Thompson , H.B. Dietrich , J.M. Eridon . Atomic profiles and electrical characteristics of very high energy Si implants in GaAs. J. Appl. Phys. , 1262 - 1265
    3. 3)
      • P.E. Thompson , H.B. Dietrich . MeV S implantation into GaAs. J. Electrochem. Soc. , 1240 - 1244
    4. 4)
      • S. Yamahata , S. Adachi . Be/P and Be/As dual implantations into AlxGa1−xAs. Appl. Phys. Lett. , 1161 - 1163
    5. 5)
      • S.M. Sze . (1981) , Physics of semiconductor devices.
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