GaAs Vertical pin diode using MeV implantation

GaAs Vertical pin diode using MeV implantation

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Vertical pin diodes were fabricated using MeV Si/S coimplantation and keV Be/P coimplantation into undoped semi-insulating GaAs to obtain buried n+ and surface p+ regions, respectively. An exploratory device with a 500 × 500 μm2 junction area and a 3 μm thick intrinsic region had a break-down voltage of 70 V, reverse leakage current density of 40 μA/cm2 at 20 V, an off-state capacitance of 3.9nF/cm2 and a DC forward resistance of 2.4 Ω at 100 mA.


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