A new associative memory cell is described and analysed using SPICE3d1. The CMOS cell uses current summation to compute, in parallel, Hamming distances between the search key and each word in the memory. For 32 bit words, SPICE simulations of a 2μm process show a delay of 4ns/bit for Hamming distances less than three.
Inspec keywords: circuit analysis computing; CMOS integrated circuits; content-addressable storage; integrated memory circuits; parallel processing
Other keywords:
Subjects: Electronic engineering computing; Memory circuits; Semiconductor storage; Multiprocessing systems; CMOS integrated circuits; Computer-aided circuit analysis and design
References
-
-
1)
- S. Jones . Design, selection and implementation of a content addressable memory for a VLSI CMOS architecture. IEE Proc. E , 3 , 165 - 172
-
2)
- Current, K.W.: `A CMOS quaternary latch', Proc. Int. Symp. on Multiple Valued Logic, May 1989, p. 54–57.
-
3)
- Current, K.W.: `A quaternary logic encoder-decoder circuit design using CMOS', Proc. Int. Symp. on Multiple Valued Logic, May 1983, p. 190–195.
-
4)
- C.C. Foster . (1976) , Content addressable parallel processors.
-
5)
- J. Wakerly . , Error detecting codes, self-checking circuits and applications.
-
6)
- M. Mostomura , J. Toyoura , K. Hirata , H. Ooka , H. Yamada , T. Enomoto . A 1.2-million transistor, 33-MHz, 20-b dictionary search processor (DISP) ULSI with a 160-kb CAM. IEEE J. Solid-State Circuits , 5 , 1158 - 1165
-
7)
- J.P. Wade , C.G. Sodini . A ternary content addressable search engine. IEEE J. Solid-State Circuits , 4 , 1003 - 1013
-
8)
- S.R. Jones , I.P. Jalowiecki , S.J. Hedge , R.M. Lea . A 9-kbit associative memory for high-speed parallel processing applications. IEEE J. Solid-State Circuits , 2 , 543 - 548
-
9)
- K. Hwang , F.A. Briggs . (1984) , Computer architecture and parallel processing.
-
10)
- C.A. Finnila , H.H. Love . The associative array processor. IEEE Trans. , 2 , 112 - 125
-
11)
- L.T. Clark , R.O. Grondin . A pipelined associative memory implemented in VLSI. IEEE J. Solid-State Circuits , 1 , 28 - 34
-
1)
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