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Error correction technique for multivalued MOS memory

Error correction technique for multivalued MOS memory

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© The Institution of Electrical Engineers
Published

An error correction technique is proposed to increase the noise margin of a multivalued MOS memory. The stored voltage information is first converted to a binary representation. The noise margin of the store voltage is then increased by storing and comparing the least significant bits of the binary representation.

Inspec keywords: MOS integrated circuits; integrated memory circuits; error correction

Other keywords: stored voltage information; multivalued MOS memory; binary representation; noise margin improvement; error correction technique

Subjects: Memory circuits; Semiconductor storage; Other MOS integrated circuits

References

    1. 1)
      • Lee, E., Gulak, G.: `A CMOS field programmable analog array', IEEE ISSCC Dig. of Technical Papers, 1991, p. 186–187.
    2. 2)
      • B. Hochet . Multivalued MOS memory for variable-synapse neural networks. Electron. Lett. , 10 , 669 - 670
    3. 3)
      • D.B. Schwartz , R.E. Howard , W.E. Hubbard . A programmable analog neural network chip. IEEE J. Solid State Circuits , 2 , 313 - 319
    4. 4)
      • B. Hochet , V. Peiris , S. Abdo , M.J. Declercq . Implementation of a learning Kohonen neuron based on a new multilevel storage technique. IEEE J. Solid State Circuits , 3 , 262 - 267
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