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Error correction technique for multivalued MOS memory

Error correction technique for multivalued MOS memory

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An error correction technique is proposed to increase the noise margin of a multivalued MOS memory. The stored voltage information is first converted to a binary representation. The noise margin of the store voltage is then increased by storing and comparing the least significant bits of the binary representation.

References

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      • Lee, E., Gulak, G.: `A CMOS field programmable analog array', IEEE ISSCC Dig. of Technical Papers, 1991, p. 186–187.
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