Efficient VLSI digital logarithmic codecs

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Efficient VLSI digital logarithmic codecs

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N bit digital words can be logarithmically encoded and compressed to a word length of (log2n + m − 1) bit maintaining a relative accuracy of m bit over (n − m) octaves of signal level. A bit-serial VLSI coder is reported, which requires little more than a log2n counter and an output register and it has a latency of one wordlength. The bit-parallel coder can be built with less than n2 transistors and has less than n/4 gate delays. The decoder has similar properties and it expands the logarithm to an antilogarithm with n bit of dynamic range. Using these codecs, digital multiplication, division, powers and roots are reduced to additions, subtractions and shifts, respectively.

Inspec keywords: digital integrated circuits; encoding; codecs; decoding; VLSI

Other keywords: digital multiplication; logarithmic coding; powers; log2n counter; digital signal processing; decoder; output register; division; roots; bit-parallel coder; bit-serial VLSI coder; digital logarithmic codecs

Subjects: Semiconductor integrated circuits; Other digital circuits; Stations and subscriber equipment; Codes

References

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      • E. Hall , D. Lynch , S. Dwyer . Generation of products and quotients using approximate binary logarithms for digital filtering applications. IEEE Trans. , 97 - 105
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      • K. Hwang . (1979) , Computer arithmetic.
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      • MA. Gin-Kou , F.J. Taylor . Multiplier policies for digital signal processing. IEEE ASSP Mag. , 6 - 20
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