© The Institution of Electrical Engineers
A two-dimensional numerical simulation study of latch up in merged bipolar-MOS structures for BICMOS applications is presented. The results of the simulations indicate that special precautions must be exercised in designing merged transistor structures for these applications.
References
-
-
1)
-
J.B. Kuo ,
G.P. Rosseel ,
R.W. Dutton
.
Two-dimensional analysis of a merged BiPMOS device.
IEEE Trans.
,
929 -
932
-
2)
-
Technology Modeling Associates, Inc., `TMA PISCES-2B, twodimensional device analysis program, user's manual', February 1989, Technology Modeling Associates, Inc..
-
3)
-
A. Bellaouar ,
M.I. Elmasry
.
Novel merged BiCMOS circuit structures.
Electron. Lett.
,
1555 -
1556
-
4)
-
N. Rovedo ,
S. Ogura ,
J. Acocella ,
K. Barnes ,
A. Dally ,
T. Yanagisawa ,
C. Ng ,
J. Burkhardt ,
E. Valsamakis ,
J. Hamers ,
T. Buti ,
C. Richwine
.
(1990)
Process design for merged complementary BiCMOS, 1990 IEDM Dig. Tech. Papers.
-
5)
-
P. Raje ,
R. Ritts ,
K. Cham ,
J. Plummer ,
K. Saraswat
.
(1991)
MBiCMOS: A device and circuit technique scalable to the submicron, sub-2V regime, ISSCC Dig. Tech. Papers.
-
6)
-
F. Walczyk ,
J. Rubinstein
.
(1983)
A merged CMOS/bipolar VLSI process, 1983 IEDM Dig. Tech. Papers.
-
7)
-
Technology Modeling Associates, Inc., `TMA SUPREMO-3, one dimensional process analysis program, user's manual', December 1988, Technology Modeling Associates, Inc..
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19910702
Related content
content/journals/10.1049/el_19910702
pub_keyword,iet_inspecKeyword,pub_concept
6
6