MOS implementation of winner-take-all network with application to content-addressable memory

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MOS implementation of winner-take-all network with application to content-addressable memory

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© The Institution of Electrical Engineers
Published

Implementation of a winner-take-all (WTA) network suitable for implementing a nearest-match content-addressable memory (CAM) is presented. The resolution of the network in differentiating between words with large bit mismatches is presented. A measure of the time performance of the network is also given. A fully functional 16 word by 12 bit chip has been fabricated through MOSIS using 2 μm double-metal CMOS technology.

Inspec keywords: content-addressable storage; CMOS integrated circuits; integrated memory circuits

Other keywords: content-addressable memory; bit mismatches; winner-take-all network; MOSIS; double-metal CMOS technology; time performance

Subjects: Memory circuits; CMOS integrated circuits; Semiconductor storage

References

    1. 1)
      • J. Lazzaro , D.S. Touretzky . (1989) Winner-take-all networks of O(N) complexity, Advances in neural information processing systems I.
    2. 2)
      • R.P. Lippman . An introduction to computing with neural nets. IEEE ASSP Magazine , 2 , 4 - 22
    3. 3)
      • Jalaleddine, S.M.S.: `Integrated circuit implementation of associative memories with neural inspired best match and relational search capabilities', December 1990, Ph.D. Dissertation, Oklahoma State University.
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