New algorithm for testing random access memories

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New algorithm for testing random access memories

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© The Institution of Electrical Engineers
Published

A linear time complexity algorithm to test RAMs is presented. The algorithm requires only 7n read/write operations and provides an extensive fault coverage. The main advantage of the proposed scheme is that a small test time can be achieved.

Inspec keywords: integrated memory circuits; integrated circuit testing; random-access storage

Other keywords: testing random access memories; small test time; fault coverage; RAM chips testing; 7 n read/write operations; linear time complexity algorithm

Subjects: Manufacturing processes; Production facilities and engineering; Memory circuits; Semiconductor storage; Semiconductor integrated circuits; Testing

References

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