State assignment using programmable counters
State assignment using programmable counters
- Author(s): M. Davio and M. Ciesielski
- DOI: 10.1049/el:19910006
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- Author(s): M. Davio 1 and M. Ciesielski 2
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View affiliations
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Affiliations:
1: Philips Research, Louvain-la-Neuve, Belgium
2: Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
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Affiliations:
1: Philips Research, Louvain-la-Neuve, Belgium
- Source:
Volume 27, Issue 1,
3 January 1991,
p.
9 – 10
DOI: 10.1049/el:19910006 , Print ISSN 0013-5194, Online ISSN 1350-911X
The use of programmable counters in the state assignment of finite state machines is discussed. A systematic method is presented for maximising the use of such a counter and for minimising accordingly the storage of next state codes.
Inspec keywords: logic circuits; state assignment; finite automata; codes; logic design
Other keywords:
Subjects: Switching theory; Logic circuits; Automata theory
References
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1)
- Amman, R., Eschermann, B., Baitinger, U.G.: `PLA based finite state machines using Johnson counters as state memories', IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1988, p. 267–270, ICCD 88.
-
2)
- J. Hartmanis , R.E. Stearns . (1966) , Algebraic structure theory of sequential machines.
-
3)
- R. Amman , U.G. Baitinger . (1987) , New state assignment algorithms for FSM using counters and multiple PLA/ROM structures.
-
4)
- G. de Micheli , R.K. Brayton , A. Sangiovanni-Vincentelli . Optimal state assignment for finite state machines. IEEE Trans. , 3 , 269 - 284
-
5)
- S. Devadas , H.-K.T. Ma , A.R. Newton , A. Sangiovanni-Vincentelli . MUSTANG: State assignment of finite state machines targeting multilevel logic implementation. IEEE Trans. , 12 , 1290 - 1300
-
6)
- M. Paull , S. Unger . Minimizing the number of states in incompletely specified sequential circuits. IEEE Trans. , 356 - 367
-
7)
- S. Yang , M.J. Ciesielski . Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
-
8)
- P.L. Hammer , S. Rudeanu . (1968) , Boolean methods in operations research and related areas.
-
1)
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