Novel gate voltage ramping technique for the characterisation of metal-oxide-semiconductor capacitor charge trapping properties

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Novel gate voltage ramping technique for the characterisation of metal-oxide-semiconductor capacitor charge trapping properties

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© The Institution of Electrical Engineers
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A novel technique is proposed to characterise the charge trapping properties of MOS capacitors by using the gate voltage ramping test. The parameter I=1−Ig(t)/Is(t + Δt) measured during gate voltage ramping reveals the dielectric charge trapping characteristics. Positive charge trapping before dielectric breakdown was observed using this technique. A comparison between I and flatband voltage shift, ΔVfb, indicates that I gives the same information as ΔVfb does at high stress fluences.

Inspec keywords: capacitors; electron energy states of amorphous solids; metal-insulator-semiconductor devices

Other keywords: dielectric charge trapping characteristics; gate voltage ramping technique; flatband voltage shift; gate voltage ramping test; charge trapping properties of MOS capacitors

Subjects: Capacitors; Metal-insulator-semiconductor structures; Electronic structure of amorphous and glassy solids; Insulated gate field effect transistors; Electrical properties of metal-insulator-semiconductor structures

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