Novel content addressable memory

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Novel content addressable memory

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© The Institution of Electrical Engineers
Published

The design and performance of a content addressable memory (CAM) LSI using a newly developed cell circuit is presented. The LSI has all the functions necessary to implement a high-speed data searching system and is fabricated using a 3 μm CMOS double-metallisation process. A cycle time of 60 ns with the basic associative operation taking 20 ns has been measured.

Inspec keywords: content-addressable storage; integrated memory circuits; large scale integration; CMOS integrated circuits

Other keywords: CMOS double-metallisation process; high-speed data searching system; 3 micron; parallel processing; cycle time; 60 ns; associative operation; LSI; CAM; content addressable memory; 20 ns; cell circuit

Subjects: CMOS integrated circuits; Memory circuits; Semiconductor storage

References

    1. 1)
      • S.R. Jones , R.M. Lea , G. Saucier , J. Trilhe . (1986) Content addressable memories for WSI associative string processor (WASP) devices, Wafer scale integration.
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19890359
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