Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Parallel processing for Viterbi algorithm

Parallel processing for Viterbi algorithm

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© The Institution of Electrical Engineers
Published

Dual-dimensional parallelisation for the Viterbi algorithm is exploited. That is, parallelisation of the decoding procedures within each stage of the trellis and parallelisation of the decoding procedures are expanded to consecutive stages without excessive path memories. Since an arbitrary number of stages can be parallelised, the trade-off between computation speed and degree of integration can be adjusted as required.

Inspec keywords: decoding; parallel architectures; VLSI; microcomputer applications; parallel processing; cellular arrays

Other keywords: degree of integration; expanded to consecutive stages; VLSI systolic arrays; decoding procedures; Viterbi algorithm; Viterbi decoding; 2D parallel processing; trellis search parallelism; trade-off; arbitrary number of stages; computation speed

Subjects: Microprocessors and microcomputers; Communications computing; Computer architecture; Semiconductor integrated circuits

References

    1. 1)
      • C. Mead , L. Conway , C. Seitz . (1980) , Introduction to VLSI systems.
    2. 2)
      • I.S. Reed , T.K. Truong , J.M. Jensen , I.S. Hsu . The VLSI design of an error-trellis syndrome decoder for certain convolutional codes. IEEE Trans. , 742 - 754
    3. 3)
      • Chang, C.Y., Yao, K.: `Viterbi decoding by systolic array', Proc. Twenty-Third Annu. Allerton Conf. Commun., Cont. Comput., 2–4 October 1985, Monticello , Allerton House, p. 430–439, IL.
    4. 4)
      • S.Y. Kung . (1988) , VLSI array processors.
    5. 5)
      • E. Horowitz , S. Sahni . (1978) , Fundamentals of computer algorithms.
    6. 6)
      • A.J. Viterbi , J.K. Omura . (1979) , Principles of digital communication and coding.
    7. 7)
      • P.G. Gulak , E. Shwedyk . VLSI structures for Viterbi receivers: Part I—General theory and applications. IEEE J. Select. Areas Commun.
    8. 8)
      • P.G. Gulak , T. Kailath . Locally connected VLSI architectures for the Viterbi algorithm. IEEE J. Select. Areas Commun. , 527 - 537
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19880745
Loading

Related content

content/journals/10.1049/el_19880745
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address