High-speed accurate CMOS comparator

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High-speed accurate CMOS comparator

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A high-speed CMOS comparator for A/D convertors is discussed. The circuit has high resolution (better than 5 mV) in combination with high speed (clock frequencies up to 50 MHz). The advantage of the proposed structure is that no clock feedthrough is injected to the input, only one switch in a symmetrical structure is used and the effect of any current biasing on the comparator speed has been reduced.

Inspec keywords: comparators (circuits); analogue-digital conversion; CMOS integrated circuits

Other keywords: A/D convertors; high-speed CMOS comparator; current biasing; resolution; high speed; symmetrical structure; clock feedthrough; clock frequencies

Subjects: CMOS integrated circuits; A/D and D/A convertors; A/D and D/A convertors

References

    1. 1)
      • D. Salbaerts . A single chip U-interface transceiver for ISDN. IEEE J. Solid-State Circ.
    2. 2)
      • R. Koch . A 12-bit sigma-delta analog-to-digital converter with a 15 MHz clock rate. IEEE J. Solid-State Circ.
    3. 3)
      • van Peteghem, P.: `Accuracy and resolution of switched-capacitor circuits in MOS technology', June 1986, PhD dissertation, K.U. Leuven.
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