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A high-speed CMOS comparator for A/D convertors is discussed. The circuit has high resolution (better than 5 mV) in combination with high speed (clock frequencies up to 50 MHz). The advantage of the proposed structure is that no clock feedthrough is injected to the input, only one switch in a symmetrical structure is used and the effect of any current biasing on the comparator speed has been reduced.
References
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1)
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D. Salbaerts
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A single chip U-interface transceiver for ISDN.
IEEE J. Solid-State Circ.
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R. Koch
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A 12-bit sigma-delta analog-to-digital converter with a 15 MHz clock rate.
IEEE J. Solid-State Circ.
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3)
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van Peteghem, P.: `Accuracy and resolution of switched-capacitor circuits in MOS technology', June 1986, PhD dissertation, K.U. Leuven.
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19880699
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content/journals/10.1049/el_19880699
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