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1887

Novel CMOS latch with clock hysteresis

Novel CMOS latch with clock hysteresis

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A latch circuit is described which tolerates the use of slow and skewed clock signals. The low-complexity circuit has been shown to provide a safe alternative to the use of non-overlapping clocks, and enables the minimisation of clock interconnection and power.

References

    1. 1)
      • C.L. Seitz . (1980) System timing, Introduction to VLSI systems.
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