New clustering approach to chip floorplan using functional data

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New clustering approach to chip floorplan using functional data

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© The Institution of Electrical Engineers
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An approach to chip floorplanning utilising hierarchical and functional information derived using LSI logic design is described. The proposed approach adopts a methodological design process similar to that of expert designers. A new clustering method that can be divided into three phases, namely clustering, cluster classification and placement, is employed in this process. The prototype system is implemented based on AI techniques.

Inspec keywords: integrated circuit technology; large scale integration; logic CAD; circuit layout CAD

Other keywords: classification; AI techniques; chip floorplan; LSI logic design; computer aided design; placement; methodological design process; hierarchical information; functional data; CAD; clustering approach

Subjects: Semiconductor integrated circuits; Logic circuits; Electronic engineering computing; Computer-aided logic design; Computer-aided circuit analysis and design

References

    1. 1)
      • Heller, W.R., Sorkin, G., Maling, K.: `The planar package planner for system designers', Proc. of 19th DA conf., June 1982, p. 253–260.
    2. 2)
      • Watanabe, H., Ackland, B.: `Flute—a floorplanning agent for full custom VLSI design', Proc. of 23rd DA conf., June 1986, p. 601–607.
    3. 3)
      • Schular, D.M., Ulrich, E.G.: `Clustering and linear placement', Proc. of 9th DA workshop, June 1972, p. 50–56.
    4. 4)
      • F. Hattori , N. Shimizu , H. Tsuchiya , K. Kuwabara , T. Wasano . (1985) , Knowledge base management system (KBMS).
    5. 5)
      • K. Ueda , H. Kitazawa , I. Harada . CHAMP: chip floor plan for hierarchical VLSI layout design. IEEE Trans. , 12 - 22
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