New proposal for a multigigabit/s clock recovery IC based on a standard silicon bipolar technology

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New proposal for a multigigabit/s clock recovery IC based on a standard silicon bipolar technology

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© The Institution of Electrical Engineers
Published

A clock recovery IC for optical fibre communication at multigigabit/s is proposed. The clock frequency extracted corresponds to half the bit rate. The 2:1 frequency division is carried out by a double balanced mixer and the frequency selection by an SAW filter. Circuit simulations are based on a standard 2 μm silicon bipolar technology. The circuit was optimisd at 3.4 Gbit/s for a power consumption of 220 mW with a 1.7 GHz SAW filter (Q = 340). The dynamic clock phase jitter, estimated from circuit simulations, is less than 0.5°. Circuit simulations predict that the operating bit rate may be exended up to 4.5 Gbit/s.

Inspec keywords: bipolar integrated circuits; elemental semiconductors; surface acoustic wave devices; silicon; optical communication equipment; solid-state microwave circuits; semiconductor technology

Other keywords: clock recovery IC; SAW filter; 3.4 Gbit/s; operating bit rate; dynamic clock phase jitter; semiconductors; frequency selection; power consumption; Si bipolar chip; 1.7 GHz; frequency division; optical fibre communication; Q-factor 340; 220 mW

Subjects: Passive filters and other passive networks; Solid-state microwave circuits and devices; Optical communication; Bipolar integrated circuits; Elemental semiconductors; Acoustic wave devices

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