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High-speed GaAs 4×4-bit parallel multiplier using super capacitor FET logic

High-speed GaAs 4×4-bit parallel multiplier using super capacitor FET logic

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An ECL-compatible 4×4-bit parallel multiplier implemented using the GaAs D-MESFET logic approach of super capacitor FET logic has been realised. Fully functional circuit operation was obtained with a worst-case multiplication time of 1.4 ns (88 ps/gate) at 1.6 W dissipation, the best speed ever reported for a multiplier fabricated with GaAs MESFET technology.

References

    1. 1)
      • J. Sone , J. Tsai , A. Hiroyuki . A 280-ps Josephson 4-bit × 4-bit parallel multiplier. IEEE J. Solid-State Circuits , 1056 - 1060
    2. 2)
      • H. Chung , G. Lee , K. Tan , K. Betz , P. Vold . High speed ultra-low power GaAs MESFET 5×5 multipliers. Can. J. Phys. , 15 - 18
    3. 3)
      • J. Sitch . Comparison of FET logic families for a GaAs DMESFET process. Can. J. Phys.
    4. 4)
      • Schlier, A.R., Pei, S.S., Shan, N.J., Tu, C.W., Mahoney, G.E.: `A high speed 4×4 bit multiplier using selectively doped heterostructure transistors', IEEE GaAs IC symposium, 1985, p. 91–93.
    5. 5)
      • D. Arch , B. Betz , P. Vold , J. Abrokwah , N. Cirillo . A self-aligned gate superlattice (Al, Ga)As/n+-GaAs MODFET 5×5-bit parallel multiplier. IEEE Electron Device Lett. , 700 - 702
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