Certain variations of the familiar serial/parallel multiplier architecture produce full-precision serial output at low area cost. However, logic gates included to form partial products and clear the accumulator between product calculations contribute to hardware complexity, and impair performance. A novel multiplication architecture—the ‘automultiplier’— pipelines the formation of partial products and dispenses with gating in the critical sum and carry paths internal to the array, reducing the computational element to the minimum full-adder at each stage. The automultiplier is so-called because its accumulator is automatically reset in the final cycles of a product calculation, and thus requires no internal hardware for initialisation. The resulting low-complexity multiplier array may sustain maximally high clocking rates.