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Serial-data computation on twin pipelines

Serial-data computation on twin pipelines

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© The Institution of Electrical Engineers
Published

The letter describes a novel two-wire data representation for bit-serial architectures. The technique offers twice the data throughput of conventional bit-serial systems at a cost of much less than twice the hardware. In some cases less hardware than the conventional one-wire representation can be used to implement the two-wire representation.

Inspec keywords: computer architecture; logic design; VLSI

Other keywords: bit-serial architectures; serial data computation; twin pipelines; twice data throughput; two-wire data representation

Subjects: Logic and switching circuits; Computer architecture; Logic circuits; Semiconductor integrated circuits

References

    1. 1)
      • McGregor, M.S., Denyer, P.B., Murray, A.F.: `A single-phase clocking scheme for CMOS VLSI', To be presented at conference on advanced research in VLSI, March 1987, USA, Center for Integrated Systems, Stanford University, p. 23–25.
    2. 2)
      • P. Denyer , D. Renshaw . (1985) , VLSI signal processing: a bit-serial approach.
    3. 3)
      • C. Mead , L. Conway , C. Seitz . (1980) , Introduction to VLSI systems.
    4. 4)
      • Smith, S.G., McGregor, M.S., Denyer, P.B.: `Techniques to increase the computational throughput of bit-serial architectures', Proc. IEEE ICASSP'87, April 1987, p. 6–9, To be published in.
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