High-accuracy pipeline A/D convertor configuration

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High-accuracy pipeline A/D convertor configuration

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A novel pipeline A/D convertor configuration is proposed which appears to have some speed and accuracy advantages over earlier schemes. Circuits are also given for the compensation of the DC offset voltages of the input S/H stages, and for increasing the time available for signal acquisition.

Inspec keywords: error compensation; pipeline processing; analogue-digital conversion

Other keywords: A/D converter; DC offset voltages; compensation; pipeline configuration; ADC; input sample/hold stages

Subjects: A/D and D/A convertors; A/D and D/A convertors

References

    1. 1)
      • Blauschild, R.A.: An 8 b 50 ns monolithic A/D converter with internal S/H, 1983, New York, NY, p. 178–179.
    2. 2)
      • W.C. Black , D.A. Hodges . Time interleaved converter arrays. IEEE J. Solid-State-Circuits , 1022 - 1029
    3. 3)
      • Masuda, S., Kitamura, Y., Ohya, S., Kituchi, M.: `A CMOS pipieline algorithmic converter', Proceedings of IEEE custom integrated circuits conference, 1984, Rochester, NY, p. 559–562.
    4. 4)
      • Martin, K.: `A high-speed, high accuracy pipeline A/D convertor', Conference record of Asilomar conference on circuits, systems and computers, 1981, CA, Pacific Grove, p. 489–492.
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