Novel switched logic CMOS latch building block

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Novel switched logic CMOS latch building block

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© The Institution of Electrical Engineers
Published

A six-transistor static CMOS building block for latches is proposed, based on the use of PMOS and NMOS switches. It is shown how latches can be built from this building block.

Inspec keywords: logic design; integrated logic circuits; CMOS integrated circuits

Other keywords: NMOS switches; logic IC; PMOS switches; D-latch; six transistor configuration; logic design; building block; switched logic CMOS latch

Subjects: CMOS integrated circuits; Logic and switching circuits; Logic circuits; Logic design methods

References

    1. 1)
      • M.C. Graf . Latch element design. IBM Tech. Disclosure Bull. , 6463 - 6466
    2. 2)
      • L. Spaanenburg . A methodology for the fast and testable implementation of state diagram specifications. IEEE J. Solid-State Circuits
    3. 3)
      • J.A. Hiltebeitel . CMOS XOR. IBM Tech. Disclosure Bull. , 5470 - 5471
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