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Below 10 ps/gate operation with buried p-layer SAINT FETs

Below 10 ps/gate operation with buried p-layer SAINT FETs

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GaAs SAINT FETs with a p-layer buried under the active layer have achieved below 10 ps/gate (9.9 ps/gate) operation for the first time in semiconductor devices. The p-layer formed by Be+ implantation is completely depleted by the built-in potential. It has successfully alleviated the short channel effects without increasing parastic capacitance.

References

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      • Ohmori, M.: `Gallium arsenide integrated circuit', 11th International symposium on gallium arsenide and related compounds, 1984, Biarritz.
    2. 2)
      • K. Yamasaki , K. Asai , T. Mizutani , K. Kurumada . Self-align implantation for n+-layer technology (SAINT) for high-speed GaAs ICs. Electron. Lett. , 119 - 121
    3. 3)
      • Yamasaki, K., Kato, N., Matsuoka, Y., Ohwada, K.: `EB-writing self-aligned GaAs MESFETs for high-speed LSIs', Technical digest of 1982 international electron devices meeting, 1982, San Francisco, p. 166–169.
    4. 4)
      • Yamasaki, K., Hirayama, M.: `Theoretical approach in gate shortening of ', National conference record on semiconductor and material of IECE Japan, 1983, p. 67.
    5. 5)
      • Matsumoto, K., Hashizume, N., Atoda, N.: `Sub-micron-gate self-aligned GaAs FET with ', IEEE 42nd device research conference, 1984, Santa Barbara, VIB-5.
    6. 6)
      • Nakamura, H., Tsunotani, M., Sano, Y., Nonaka, T., Ishida, T., Kaminishi, K.: `The effect of substrate purity on short-channel effects of GaAs MESFETs', Extended abstracts of 16th conference on solid-state devices and materials, 1984, Kobe, p. 395–398.
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