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Low-resistance submicrometre gates used for self alignment

Low-resistance submicrometre gates used for self alignment

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A novel gate fabrication technique useful for MESFETs is presented. The gates have submicrometre dimensions with an extremely low ohmic resistance and are used for self alignment. Simple optical projection lithography and electroplating techniques are needed. The resulting gates have proved to be mechanically strong.

References

    1. 1)
      • K. Yamasaki , K. Asai , K. Kuramanda . GaAs LSI-directed MESFETs with self aligned implantation for n+-layer technology (SAINT). IEEE Trans. , 1772 - 1777
    2. 2)
      • Y. Imai . A sub-half-micron gate-length GaAs MESFET with new gate structure. IEEE Electron Device Lett. , 99 - 101
    3. 3)
      • P.C. Chao . A high aspect-ratio 0.1 micron gate technique for low-noise MESFET. IEEE Electron Device Lett. , 24 - 26
    4. 4)
      • H.M. Levy , R.E. Lee . Self-aligned submicron gate digital GaAs integrated circuits. IEEE Trans. , 102 - 103
    5. 5)
      • G. Romero . Fabrication of submicrometer gold lines using optical lithography and high growth rate electroplating. IEEE Electron. Device Lett. , 210 - 212
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