Fault signature effectiveness of microcomputer address bus

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Fault signature effectiveness of microcomputer address bus

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The letter presents the analysis of the effectiveness of compact testing of a microcomputer address bus with the assumed fault model SA1 and SA0, assuming that the testing schemes use a linear feedback shift register LFSR with a prime characteristic polynomial p(x) of degree n≥2.

Inspec keywords: fault location; computer testing; logic testing; computer interfaces

Other keywords: linear feedback shift register; fault signature effectiveness; fault model; microcomputer address bus; prime characteristic polynomial

Subjects: Logic design methods; Computer interfaces

References

    1. 1)
      • Hassan, S.Z., McCluskey, E.J.: `Parallel signature analyzers—Detection capability and extensions', Digest of Papers COMPCON, 28th February–3rd March 1983, p. 440–445, Spring 1983.
    2. 2)
      • ‘Guidelines for signature analysis—Understanding the signature measurement’, Hewlett-Packard Application Note, 222-4.
    3. 3)
      • A. Hlawiczka . (1984) Binary implemented compression of multiple-valued data serial streams, ISMVL'84.
    4. 4)
      • J.E. Smith . Measures of the effectiveness of fault signature analysis. IEEE Trans. , 510 - 514
    5. 5)
      • R.A. Frochwerk . Signature analysis: A new digital field service method. Hewlett-Packard J. , 2 - 8
    6. 6)
      • Hawiczka, A., Kubica, H.: `Method of increasing the probability of detecting errors for signature analysis', Proc. of 4th Int. Conf. on fault-tolerant systems and diagnostics, September 1981, Brno, Czechoslavakia.
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