Low-noise operational amplifiers using bipolar input transistors in a standard metal gate CMOS process

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Low-noise operational amplifiers using bipolar input transistors in a standard metal gate CMOS process

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Two low-noise operational amplifiers have been designed. The amplifiers include a bipolar input stage which gives the advantage against conventional CMOS amplifiers of low noise and low offset. The op-amplifiers also show a low input current compared with other bipolar amplifiers.

Inspec keywords: differential amplifiers; field effect integrated circuits; operational amplifiers; linear integrated circuits

Other keywords: differential amplifiers; input stage; bipolar input transistors; low-noise operational amplifiers; linear IC; standard metal gate CMOS process; low offset

Subjects: Amplifiers; CMOS integrated circuits

References

    1. 1)
      • E. Vittoz . MOS transistors operated in the lateral bipolar mode and their application in CMOS technology. IEEE J. Solid-State Circuits , 273 - 279
    2. 2)
      • S. Christensson , I. Lundstrom , C. Svensson . Low frequency noise in MOS transistors, 1 Theory. Solid-State Electron. , 797 - 812
    3. 3)
      • P.A. Sullivan , D.L. Ellsworth , Jiang Xiang-Liu , Deng Pei-De . High performance bipolar transistors in a CMOS process. IEEE Trans. , 1679 - 1680
    4. 4)
      • D. Senderowicz , D.A. Hodges , P.R. Gray . High-performance NMOS operational amplifiers. IEEE J. Solid-State Circuits , 760 - 766
    5. 5)
      • C.S. Yue , C.C. Huang , J.W. Schrankler , N.F. Pu , G.D. Kirchner , C. Rahn . Improved bipolar transistor performance in a VLSI CMOS process. IEEE Electron Device Lett. , 294 - 296
    6. 6)
      • Deqrauwe, M.G., Sansen, W.M.C.: `Current efficiency of CMOS OP-amps', Proceedings of ESSCIRC 83, 20–23 September 1983, Lausanne.
    7. 7)
      • Vittoz, E.: `Application of MOS transistors operated in the lateral bipolar mode in CMOS technology', Proceedings of ESSCIRC 82, 1982, Brussels, p. 29–32.
    8. 8)
      • J.E. Solomon . The monolithic OP amp: A tutorial study. IEEE J. Solid-State Circuits , 314 - 332
    9. 9)
      • G. Zimmer , B. Hoefflinger , J. Schneider . A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital system. IEEE Trans. , 390 - 396
    10. 10)
      • O. Olesen , C. Svensson . Norchip, a silicon brokers model. Integration
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