High-transconductance self aligned GaAs MESFET using implantation through an AlN layer

Access Full Text

High-transconductance self aligned GaAs MESFET using implantation through an AlN layer

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Tungsten-silicide-gate self aligned GaAs MESFETs were fabricated on a very thin channel layer formed by implantation through an AlN layer on a semi-insulating GaAs substrate. Transconductance of the through-implanted MESFETs showed a 30 to 50% increase as compared with that of conventional self aligned MESFETs, and reached its maximum value at 300 mS/mm for 1μm-gate-length FETs.

Inspec keywords: ion implantation; III-V semiconductors; Schottky gate field effect transistors; gallium arsenide; semiconductor doping

Other keywords: self aligned structure; semiconductor doping; channel layer; WSi2 gate; AlN layer; transconductance; GaAs MESFET; III-V semiconductors

Subjects: Semiconductor doping; Other field effect devices

References

    1. 1)
      • R.A. Kiehl , P.G. Flahive , S.H. Wemple , H.M. Cox . Direct-coupled GaAs ring oscillators with self-aligned gates. IEEE Electron Device Lett. , 325 - 326
    2. 2)
      • G.W. Taylor , H.M. Darley , R.C. Frye , P.K. Chatterjee . A device model for an ion-implanted MESFET. IEEE Trans. , 172 - 182
    3. 3)
      • S. Okamura , H. Nishi , T. Inada , H.L. Hashimoto . AIN Capped annealing of Si implanted semi-insulating GaAs. Appl. Phys. Lett. , 689 - 690
    4. 4)
      • Eden, R.C.: `GaAs integrated circuits, MSI status and VLSI prospects', IEDM Tech. Digest, December 1978, p. 6–11.
    5. 5)
      • K. Yamasaki , K. Asai , K. Kurumada . GaAs LSI-directed MESFETs with self-aligned implantation for n+-layer technology (SAINT). IEEE Trans. , 1772 - 1777
    6. 6)
      • Nakayama, Y., Suyama, K., Shimizu, H., Yokoyama, N., Shibatomi, A., ishikawa, H.: `A GaAs 16 × 16b parallel multiplier using self-alignment technology', ISSCC Digest of Technical Papers, February 1983, p. 48–49.
    7. 7)
      • Yokoyama, N., Ohnishi, T., Onodera, H., Shinoki, T., Shibatomi, A., Ishikawa, H.: `A GaAs 1 K. static RAM using tungsten-silicide gate self-alignment technology', ISSCC Digest of Technical Papers, February 1983, p. 44–45.
    8. 8)
      • H.M. Levy , R.E. Lee . Self-aligned submicron gate digital GaAs integrated circuits. IEEE Electron Device Lett. , 102 - 104
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19840032
Loading

Related content

content/journals/10.1049/el_19840032
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading