Method to sequentially address a large memory, suitable for LSI implementation

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Method to sequentially address a large memory, suitable for LSI implementation

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© The Institution of Electrical Engineers
Published

A method to sequentially generate addresses to an external memory is described. The method which is based on a PRBS-generator minimises area and power consumption and maximises speed when used in IC design. The method has been tested in a dynamic memory-controller chip which was fabricated in metal gate CMOS technology.

Inspec keywords: large scale integration; integrated memory circuits; random-access storage; field effect integrated circuits

Other keywords: sequentially address; PRBS-generator; dynamic memory-controller chip; metal gate CMOS technology; RAM; LSI implementation; IC design; pseudorandom binary sequence; external memory

Subjects: Memory circuits; CMOS integrated circuits; Semiconductor storage

References

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      • A. Gill . (1966) , Linear sequential circuits.
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      • J.L. Massey . Shift-register synthesis and BCH decoding. IEEE Trans. , 122 - 127
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      • B. Hofflinger . , Grossintegration.
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      • Sevnsson, C., Sundblad, R.: `A multi project course at Linkoeping University', LiTH-IFM-IS-78, Internal report, 1981.
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