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Method to sequentially address a large memory, suitable for LSI implementation

Method to sequentially address a large memory, suitable for LSI implementation

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A method to sequentially generate addresses to an external memory is described. The method which is based on a PRBS-generator minimises area and power consumption and maximises speed when used in IC design. The method has been tested in a dynamic memory-controller chip which was fabricated in metal gate CMOS technology.

References

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      • J.L. Massey . Shift-register synthesis and BCH decoding. IEEE Trans. , 122 - 127
    2. 2)
      • A. Gill . (1966) , Linear sequential circuits.
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      • B. Hofflinger . , Grossintegration.
    4. 4)
      • Sevnsson, C., Sundblad, R.: `A multi project course at Linkoeping University', LiTH-IFM-IS-78, Internal report, 1981.
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