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Computer simulation of an oxide walled emitter STL gate

Computer simulation of an oxide walled emitter STL gate

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© The Institution of Electrical Engineers
Published

A Schottky transistor logic (STL) gate is studied using computer simulation. The relation between propagation delay time and the spacing between the diffused emitter and the isolation oxide is shown to be such that an optimum spacing exists.

Inspec keywords: digital simulation; integrated logic circuits; bipolar integrated circuits; logic gates

Other keywords: STL gate; computer simulation; propagation delay; Schottky transistor logic; isolation oxide; diffused emitter

Subjects: Logic circuits; Electronic engineering computing; Bipolar integrated circuits

References

    1. 1)
      • Sloan, B.J.: `STL technology', Intl. Electron Devices Meeting, Digest, December 1979, p. 324–327.
    2. 2)
      • Vlach, M.: `WATAND user's manual version V1.09', UW EE 82-01, Technical report, January 1982.
    3. 3)
      • Teene, A.R.: `WATPAC—A computer aided design package for digital integrated circuits', 1981, M.A.Sc. thesis, University of Waterloo, Elect. Eng. Dept..
    4. 4)
      • Roulston, D.J.: `Discrete and integrated bipolar device analysis using the BIPOLE fast computer program', Proceedings 1980 IEEE Custom Integrated Circuits Conference, May 1980, , p. 2–6.
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