© The Institution of Electrical Engineers
A GaAs 256×1-bit static RAM with 2000 FETs organised in E/D-type DCFL circuits was successfully fabricated. A planar device structure was realised by using selective ion implantation and dielectric intermediate lift-off technology. The access time and the power dissipation were 50 ns and 9.4 mW, respectively.
References
-
-
1)
-
Lee, F.S., Eden, R.C., Long, S.I., Welch, B.M., Zucca, R.: `High-speed LSI GaAs integrated circuits', 1980 Int. Conf. Circuits and Computors Tech. Digest, p. 697–700.
-
2)
-
Asai, K., Ino, M., Kurumada, K., Kawasaki, Y., Ohmori, M.: `GaAs E/D FET technology for applications to static RAM', 1981 Int. Symp. GaAs and Related Compounds, .
-
3)
-
W.E. Spicer ,
I. Lindau ,
P. Skeath ,
C.Y. Su
.
Unified defect model and beyond.
J. Vac. Sci. & Technol.
,
1019 -
1027
-
4)
-
Suyama, K., Kusakawa, H., Okamura, S., Yamamura, S., Fukuta, M.: `GaAs LSI for high-speed data processing', paper 4, Res. Abst. 1980 GaAs IC Symp., .
-
5)
-
K. Yamasaki ,
K. Asai ,
T. Mizutani ,
K. Kurumada
.
Self-align implantation for n+−layer technology (SAINT) for high-speed GaAs ICs.
Electron. Lett.
,
3 ,
119 -
121
-
6)
-
Bert, G., Morin, J.P., Nuzillat, G., Arnodo, C.: `High speed GaAs static random access memory', paper 4, Res. Abst. 1981 GaAs IC Symp., .
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19820204
Related content
content/journals/10.1049/el_19820204
pub_keyword,iet_inspecKeyword,pub_concept
6
6