GaAs 256-bit static RAM

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GaAs 256-bit static RAM

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© The Institution of Electrical Engineers
Published

A GaAs 256×1-bit static RAM with 2000 FETs organised in E/D-type DCFL circuits was successfully fabricated. A planar device structure was realised by using selective ion implantation and dielectric intermediate lift-off technology. The access time and the power dissipation were 50 ns and 9.4 mW, respectively.

Inspec keywords: gallium arsenide; III-V semiconductors; integrated memory circuits; field effect integrated circuits; ion implantation; random-access storage

Other keywords: dielectric intermediate lift-off technology; planar device structure; access time; GaAs 256-bit static RAM; selective ion implantation; E/D-type DCFL circuits; power dissipation; MESFET; FETs

Subjects: Memory circuits; Other field effect integrated circuits; Semiconductor storage

References

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      • Lee, F.S., Eden, R.C., Long, S.I., Welch, B.M., Zucca, R.: `High-speed LSI GaAs integrated circuits', 1980 Int. Conf. Circuits and Computors Tech. Digest, p. 697–700.
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      • Asai, K., Ino, M., Kurumada, K., Kawasaki, Y., Ohmori, M.: `GaAs E/D FET technology for applications to static RAM', 1981 Int. Symp. GaAs and Related Compounds, .
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      • W.E. Spicer , I. Lindau , P. Skeath , C.Y. Su . Unified defect model and beyond. J. Vac. Sci. & Technol. , 1019 - 1027
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      • Suyama, K., Kusakawa, H., Okamura, S., Yamamura, S., Fukuta, M.: `GaAs LSI for high-speed data processing', paper 4, Res. Abst. 1980 GaAs IC Symp., .
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      • K. Yamasaki , K. Asai , T. Mizutani , K. Kurumada . Self-align implantation for n+−layer technology (SAINT) for high-speed GaAs ICs. Electron. Lett. , 3 , 119 - 121
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      • Bert, G., Morin, J.P., Nuzillat, G., Arnodo, C.: `High speed GaAs static random access memory', paper 4, Res. Abst. 1981 GaAs IC Symp., .
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