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Self-align implantation for n+-layer technology (SAINT) for high-speed GaAs ICs

Self-align implantation for n+-layer technology (SAINT) for high-speed GaAs ICs

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A new GaAs MESFET structure with n+-implanted layers and a self-aligned gate has been developed by dielectric lift-off technology with trilevel resist. The electrical characteristics are improved greatly by resistance reduction outside the channel under the gate. 280 mS/mm transconductance and 39.5 ps/gate propagation delay have been obtained.

References

    1. 1)
      • Asai, K., Ino, M., Kurumada, K., Kawasaki, Y., Ohmori, M.: `GaAs E/D FET technology for applications to static RAM', Proceedings of symposium on gallium arsenide and related compounds, 1981, Oiso, Japan.
    2. 2)
      • W.E. Spicer , P.W. Chye , P.R. Skeath , C.Y. Su , I. Lindau . New and unified model for Schottky barrier and III-V insulator interface states formation. J. Vac. Sci. & Technol. , 1422 - 1433
    3. 3)
      • Yamasaki, K., Asai, K., Kurumada, K.: `Reactive ion beam etching—application to GaAs integrated circuit fabrication', Proceedings of symposium on dry processes, 1981, Tokyo, p. 105–112.
    4. 4)
      • Yokoyama, N., Mimura, T., Fukuta, M., Ishikawa, M.: `A self-aligned source/drain planar device for ultrahigh-speed GaAs MESFET VLSIs', IEEE international solid-state circuits conference, 1981, New York, p. 218–219, Digest of technical papers.
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