Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Performance of a scaled Si gate n-well CMOS technology

Performance of a scaled Si gate n-well CMOS technology

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A scaled n-well CMOS technology with 40 nm gate oxide, 1 μm PMOS and 2 μm NMOS transistors has been realised with peak effective mobilities of 710 and 260 cm2V−1s−1 for electrons and holes, respectively, and available voltage gains as high as 80 for a 1 μm PMOS and 115 for a 2 μm NMOS transistor. The corresponding maximum inverter gain was 75. The inverter supply voltage range was 1.5 to 12 V and the inverter delay time was 300 ps at 5 V supply voltage.

References

    1. 1)
      • W.C. Black , R.H. McCharles , D.A. Hodges . CMOS process for high-performance analog LSI. IEDM Tech. Dig. , 331 - 334
    2. 2)
      • M. Suzuki , K. Matsumoto , E. Sugimoto , K. Takemae , H. Yamamoto . (1978) A high-speed NMOS/CMOS single-chip 16 bit microprocessor, ISSCC Dig. of Tech. Papers.
    3. 3)
      • K.K. Yu , R.C. Mark , M.T. Bohr , M. Seidenfeld , C.N. Berglund . (1981) HMOS-CMOS technology, ISSCC Dig. of Tech. Papers.
    4. 4)
      • B. Hoefflinger , H. Sbbert , G. Zimmer . Model and performance of hot-electron MOS transistors for VLSI. IEEE Trans. , 513 - 520
    5. 5)
      • B. Hoefflinger . Output characteristics of short-channel fieldeffect transistors. IEEE Trans.
    6. 6)
      • B. Hoefflinger , G. Zimmer . (1981) New CMOS technologies, Solid state devices.
    7. 7)
      • T. Ohzone , H. Shmura , K. Tsuji , T. Hirao . Silicon-gate n-well CMOS processing by full ion implantation technology. IEEE Trans. , 1789 - 1795
    8. 8)
      • W. Schemmert , L. Gabler , B. Hoefflinger . Conductance of ion-implanted buried channel MOS transistors. IEEE Trans. , 1313 - 1319
    9. 9)
      • J. Schneider , G. Zmmer , B. Hoefflinger . A compatible NMOS, CMOS metal gate process. IEEE Trans. , 832 - 836
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19810465
Loading

Related content

content/journals/10.1049/el_19810465
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address