Annealing of Si3N4-capped ion-implanted InP

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Annealing of Si3N4-capped ion-implanted InP

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© The Institution of Electrical Engineers
Published

CVD-Si3N4 layers have been used to encapsulate Se+-implanted InP during annealing in the range 550°C to 730°C. Annealing at 700°C for about 3 min produced the best electrical properties for a dose of 1×1013 Se+ cm−2, i.e. an electrical activity of 80% and and sheet mobility of 1400 cm2V−1s−1.

Inspec keywords: annealing; indium compounds; ion implantation; III-V semiconductors; selenium

Other keywords: annealing; 550degrees C to 730degrees C; CVD-Si3N4 layers; InP:Se+ III-V semiconductor; electrical activity; sheet mobility

Subjects: Doping and implantation of impurities; Cold working, work hardening; post-deformation annealing, recovery and recrystallisation; textures; Semiconductor doping; II-VI and III-V semiconductors

References

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      • J.P. Donnelly , C.E. Hurwitz . Ion-implanted n- and p-type layers in InP. Appl. Phys. Lett. , 418 - 420
    2. 2)
      • C.A. Armiento , J.P. Donnelly , S.H. Groves . p-n junction diodes in InP and In1-xGaxAsyP1-y fabricated by beryllium-ion implantation. Appl. Phys. Lett. , 229 - 231
    3. 3)
      • D. Eirug Davies , W.D. Potter , J.P. Lorenzo . Implantation and PH3 ambient annealing of InP. J. Electrochem. Soc. , 1845 - 1848
    4. 4)
      • R.K. Surridge , B.J. Sealy . , The implantation of selenium ions in GaAs at room temperature.
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