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Electrically erasable f.a.m.o.s. memory structure using avalanche injection from floating gate

Electrically erasable f.a.m.o.s. memory structure using avalanche injection from floating gate

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A new principle is proposed for an electrically erasable f.a.m.o.s. device using a simple m.o.s. technology with double polysilicon layers in which the lower (electrically floating) polysilicon gate is left undoped. Writing is accomplished by avalanche injection of electrons from a p-n junction in the substrate as in the original f.a.m.o.s. structure. Erasing proceeds by avalanche injection of electrons from the floating gate induced by voltage pulses applied to the heavily doped upper (control) gate.

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