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Gateless synchronous counters with D flip-flops

Gateless synchronous counters with D flip-flops

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© The Institution of Electrical Engineers
Published

A new approach to the state assignment problem for the synthesis of sequential switching circuits is applied to solve completely the synthesis problem of gateless counters. The necessary and sufficient condition that assures that the counter may be synthesised without gates is found. A method is developed to determine a priori if a given state table corresponds to a circuit that may be synthesised without gates.

Inspec keywords: sequential circuits; flip-flops; state assignment; counting circuits

Other keywords: gateless synchronous counters; state assignment; type-D flip flops; sequential switching circuits

Subjects: Logic and switching circuits; Sequential switching theory; Logic circuits

References

    1. 1)
      • Harrison, H.J., Story, J.R., Reinhard, E.A.: `Optimum state assignment for synchronous sequential machines with flip-flop memory', IBM technical information, .
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      • P.S. Noe , V.T. Rhyne . Optimum state assignment for the D-flip-flop. IEEE Trans. , 306 - 311
    3. 3)
      • M.E. Ulug , B.A. Bowen . A unified theory of the algebraic topological methods for the synthesis of switching systems. IEEE Trans. , 255 - 257
    4. 4)
      • J.R. Story , H.J. Harrison , E.A. Reinhard . Optimum state assignment for synchronous sequential circuits. IEEE Trans.
    5. 5)
      • D.L. Dietmeyer . (1971) , Logic design of digital systems.
    6. 6)
      • A. Abramowitz , J. Segun . (1968) , Manual handbook of mathematical functions.
    7. 7)
      • M. Phister . (1958) , Logical design of digital computers.
    8. 8)
      • J.M. Huertas , J.I. Acha . On modulus 8 gateless synchronous scalers with J-K flip-flops. Proc. IEEE , 374 - 375
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