V-groove substrate fed logic

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V-groove substrate fed logic

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© The Institution of Electrical Engineers
Published

A new substrate fed logic structure is presented which makes use of V-groove silicon etching. Experimental results are presented for the devices. A speed-power product below 1 pJ was obtained despite the large area of the test structures and the use of conventional bipolar processing. Further improvement in performance is expected by optimising the process parameters.

Inspec keywords: bipolar integrated circuits; integrated logic circuits; integrated circuit technology

Other keywords: experimental results; V-groove substrate fed logic; substrate fed I2L; speed power product below 1 pJ

Subjects: Semiconductor logic elements; Logic circuits; Bipolar integrated circuits

References

    1. 1)
      • H.H. Berger , S.F. Wiedmann . Terminal-oriented model for merged transistor logic (MTL). IEEE J. Solid-State Circuits , 211 - 217
    2. 2)
      • V. Blatt , L.W. Kennedy , P.S. Walsh , R.C.A. Ashford . Substrate fed logic-an improved form of injection logic. IEEE IEDM Tech. Dig. , 511 - 514
    3. 3)
      • P.S. Walsh , G.W. Summerling . Schottky I2L (substrate fed logic)-an optimum form of I2L. IEEE J. Solid-State Circuits , 123 - 127
    4. 4)
      • V. Blatt , P.S. Walsh , L.W. Kennedy . Substrate fed logic. IEEE J. Solid-State Circuits , 336 - 342
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