An asynchronous logic array for the realisation of logic systems with concurrency

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An asynchronous logic array for the realisation of logic systems with concurrency

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© The Institution of Electrical Engineers
Published

An array circuit able to implement any logic system described by a Petri net is presented. It uses a request acknowledge asynchronous functioning mode and constitutes a simplification of a solution proposed by Patil previously.

Inspec keywords: cellular arrays; asynchronous sequential logic

Other keywords: asynchronous logic array; cellular arrays; asynchronous sequential logic; concurrency logic systems realisation; Petri nets

Subjects: Logic circuits; Digital storage; Sequential switching theory

References

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      • D. Misunas . Petri nets and speed independent design. C.ACM , 8
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      • W.A. Clark . (1967) , Macromodular computer systems.
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      • R.M. Keller . Towards a theory of universal speed independent modules. IEEE Trans. , 1
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      • S.S. Patil , J.B. Dennis . The description and realization of digital systems. RAIRO
    5. 5)
      • Courvoisier, M.: `Etude des systèmes logiques de commande asynchrones à évolutions simultanées', 1974, Thèse d'Etat, , Toulouse.
    6. 6)
      • J.R. Jump . Asynchronous control arrays. IEEE Trans. , 10
    7. 7)
      • Cavarroc, J.C., Blanchard, M., Gillon, J.: `An approach to the modular design of industrial switching systems', IFAC symposium on discrete systems, October 1974, Riga, USSR.
    8. 8)
      • Patil, S.S.: `An asynchronous logic array', 62, Technical memo, May 1975, Project MAC.
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