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Three-valued c.m.o.s. cycling gates

Three-valued c.m.o.s. cycling gates

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© The Institution of Electrical Engineers
Published

The design of three-valued cycling gates with c.m.o.s. integrated circuits is presented. Circuits for the cycling and the inverse cycling gates prove to be simpler than those previously reported.

Inspec keywords: integrated logic circuits; ternary logic; logic gates; field effect integrated circuits

Other keywords: inverse cycling gates; ternary logic; CMOS cycling gates

Subjects: Logic and switching circuits; Logic design methods; Logic circuits; CMOS integrated circuits

References

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      • E.L. Post . Introduction to a general theory of elementary propositions. Am. J. Math. , 163 - 185
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      • J.L. Huertas , J.I. Acha , J.M. Carmona . Implementation of some ternary operations with CMOS integrated circuits. Electron. Lett. , 385 - 386
    3. 3)
      • Mouftah, H.T., Jordan, I.B.: `Integrated circuits for ternary logic', Proceedings of the international symposium on multivalued logic, May 1974, p. 285–302.
    4. 4)
      • A. Kaniel . Trilogic, a three-level logic system provides greater memory density. EDN , 80 - 83
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