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Performance evaluation of a general framing circuit using two N-stage shift registers

Performance evaluation of a general framing circuit using two N-stage shift registers

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A general algorithm is presented for computing the average number of shifts per frame period (A) of a framing circuit which checks for N consecutive data bits for possible framing bit candidacy. A simulation program has also been written to compute A for N between 2 and 8.

References

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      • W.C. Giffin . (1971) , Introduction to operations engineering.
    2. 2)
      • A.J. Cirillo , D.K. Thovson . (1972) , D2 channel bank: digital functions.
    3. 3)
      • W. Feller . (1968) , An introduction to probability theory and its applications–Vol. 1.
    4. 4)
      • Henning, H.H.: `A 96-channel PCM channel bank', IEEE International conference on communications, June 1969, p. 34-17–34-22.
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