http://iet.metastore.ingenta.com
1887

Performance evaluation of a general framing circuit using two N-stage shift registers

Performance evaluation of a general framing circuit using two N-stage shift registers

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A general algorithm is presented for computing the average number of shifts per frame period (A) of a framing circuit which checks for N consecutive data bits for possible framing bit candidacy. A simulation program has also been written to compute A for N between 2 and 8.

References

    1. 1)
      • Henning, H.H.: `A 96-channel PCM channel bank', IEEE International conference on communications, June 1969, p. 34-17–34-22.
    2. 2)
      • A.J. Cirillo , D.K. Thovson . (1972) , D2 channel bank: digital functions.
    3. 3)
      • W. Feller . (1968) , An introduction to probability theory and its applications–Vol. 1.
    4. 4)
      • W.C. Giffin . (1971) , Introduction to operations engineering.
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19770430
Loading

Related content

content/journals/10.1049/el_19770430
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address