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Modelling technique for an f.e.t. chip

Modelling technique for an f.e.t. chip

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A technique for modelling an f.e.t. chip is presented. First, the device is characterised in its 2-port S-parameters. Then, by choosing a suitable equivalent circuit and reasonable starting values, a simplex optimisation procedure is employed to obtain optimum component values for the equivalent circuit.

References

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      • S.O. Ajose , N.A. Mathews , C.S.A. Aitchison . Characteristics of coaxial-to-microstrip connector suitable for evaluation of microstrip 2-ports. Electron. Lett. , 430 - 431
    2. 2)
      • P. Benedek , P. Silvester . Equivalent capacitances for microstrip gaps and steps. IEEE Trans. , 729 - 733
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      • P. Wolf . Microwave properties of Schottky barrier field-effect transistors. IBM J. Res.& Dev. Mar , 125 - 141
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