Gigabit/s m-sequence generation

Access Full Text

Gigabit/s m-sequence generation

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A known method of generating maximum-length sequences by employing delay lines in place of shift-register elements has been realised with base-coupled logic (b.c.l.). Sequences at speeds of up to 1.2 Gbit/;s have been produced.

Inspec keywords: pulse generators; logic circuits; binary sequences

Other keywords: gigabit/s m-sequence generation; delay lines; 1.2 Gbit/s; base coupled logic

Subjects: Information theory; Pulse circuits; Digital electronics; Signal processing and detection

References

    1. 1)
      • J.T. Harvey . High-speed m-sequence generation. Electron. Lett. , 10 , 480 - 481
    2. 2)
      • Meyer, F.: `Subnanosecond base-coupled logic circuits', Proceedings of the 1st European solid state circuits conference (ESSCIRC), 1975, Canterbury, p. 32–33.
    3. 3)
      • J.R. Ball , A.H. Spittle , H.T. Liu . High-speed m-sequence generation: a further note. Electron. Lett. , 11 , 107 - 108
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19760270
Loading

Related content

content/journals/10.1049/el_19760270
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading