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Minimal transfer c.c.d. structures

Minimal transfer c.c.d. structures

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The letter introduces a new store structure, the double binary tree, which minimises the charge loss due to intercell transfers in charge-coupled-device stores. This structure offers a significant improvement over the series-parallel-series structure (currently in use) in this respect. Modification of a design parameter converts this structure to a shift register at one extreme and a random-access store at the other. Under some design constraints, a topologically efficient configuration is possible, but, with additional constraints, it is shown that the series-parallel-series structure remains optimal.

References

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      • M.G. Collet . The influence of bulk traps on the charge-transfer inefficiency of bulk charge-coupled devices. IEEE J. Solid-State Circuits , 156 - 159
    2. 2)
      • S.D. Rosenbaum . A 16384-bit high-density CCD memory. IEEE J. Solid-State Circuits , 33 - 40
    3. 3)
      • W.E. Tchan . 4096-bit serial decoded multiphase serial-parallel-serial CCD memory. IEEE J. Solid-State Circuits , 25 - 33
    4. 4)
      • (1973) , McMOS handbook.
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