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Threshold logic functions in programmable logic arrays

Threshold logic functions in programmable logic arrays

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© The Institution of Electrical Engineers
Published

Methods of implementing threshold-logic functions in programmable logic arrays are described. Use is made of the properties of the threshold functions to achieve a more efficient implementation, in terms of silicon area required, than a previously described cellular array.

Inspec keywords: threshold logic; digital integrated circuits; cellular arrays

Other keywords: threshold logic functions; programmable logic arrays; cellular array

Subjects: Pulse circuits; Digital electronics; Logic and switching circuits

References

    1. 1)
      • J.W. Jones . Array logic macros. IBM J. Res. & Devel. , 120 - 126
    2. 2)
      • S.L. Hurst . Application of multi-output threshold logic gates to digital network design. Proc. IEE , 2 , 128 - 134
    3. 3)
      • S.L. Hurst . Specifications of threshold logic gates for optimum s.s.i. logic packaging. Electron. Lett. , 514 - 515
    4. 4)
      • L.A.M. Bennett . (1974) An assessment of functional memory and its future development, Computer systems and technology.
    5. 5)
      • S.L. Hurst . Digital-summation threshold logic gates: a new circuit element. Proc. IEE , 11 , 1301 - 1307
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