http://iet.metastore.ingenta.com
1887

Threshold logic functions in programmable logic arrays

Threshold logic functions in programmable logic arrays

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Methods of implementing threshold-logic functions in programmable logic arrays are described. Use is made of the properties of the threshold functions to achieve a more efficient implementation, in terms of silicon area required, than a previously described cellular array.

References

    1. 1)
      • S.L. Hurst . Specifications of threshold logic gates for optimum s.s.i. logic packaging. Electron. Lett. , 514 - 515
    2. 2)
      • S.L. Hurst . Digital-summation threshold logic gates: a new circuit element. Proc. IEE , 11 , 1301 - 1307
    3. 3)
      • S.L. Hurst . Application of multi-output threshold logic gates to digital network design. Proc. IEE , 2 , 128 - 134
    4. 4)
      • J.W. Jones . Array logic macros. IBM J. Res. & Devel. , 120 - 126
    5. 5)
      • L.A.M. Bennett . (1974) An assessment of functional memory and its future development, Computer systems and technology.
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19760216
Loading

Related content

content/journals/10.1049/el_19760216
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address