Determinacy of computation schemata for both parallel and simultaneous operation

Access Full Text

Determinacy of computation schemata for both parallel and simultaneous operation

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© The Institution of Electrical Engineers
Published

Computation schemata represent the flow of data and control during a parallel computing process. The letter introduces the concept of inhibit branches to the control schema and shows how they may be used to ensure determinacy under simultaneous operating conditions. A determinacy algorithm is presented.

Inspec keywords: parallel processing

Other keywords: parallel computing process; control schema; determinacy algorithm; inhibit branches; simultaneous operating conditions; computation schemata

Subjects: Automata theory; Mainframes and minicomputers

References

    1. 1)
      • Rose, C.W., Bradshaw, F.T.: `The LOGOS representation system', IEEE computer conference, 1972.
    2. 2)
      • F.G. Heath . Research in progress. Comput. Aided Des. , 3 , 171 - 173
    3. 3)
      • F.G. Heath , D. Bain . Simplified method for establishing determinacy in a directed-graph control structure. Electron. Lett. , 16 - 17
    4. 4)
      • R.M. Karp , R.E. Miller . Parallel program schemata. J. Comput. & Syst. Sci. , 147 - 195
    5. 5)
      • Bain, D.: `Systematic approach to developing determinate pipeline schemata', RM/75/2, Research Memorandum, 1975.
    6. 6)
      • Howard, B.V.: `Asynchronous control circuits for directed graphs', RM/74/l, Research Memorandum, 1974.
    7. 7)
      • Howard, B.V.: `The manipulation of simple computation schemata', RM/75/6, Research Memorandum, 1975.
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19750376
Loading

Related content

content/journals/10.1049/el_19750376
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading