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Determinacy of computation schemata for both parallel and simultaneous operation

Determinacy of computation schemata for both parallel and simultaneous operation

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Computation schemata represent the flow of data and control during a parallel computing process. The letter introduces the concept of inhibit branches to the control schema and shows how they may be used to ensure determinacy under simultaneous operating conditions. A determinacy algorithm is presented.

References

    1. 1)
      • Rose, C.W., Bradshaw, F.T.: `The LOGOS representation system', IEEE computer conference, 1972.
    2. 2)
      • R.M. Karp , R.E. Miller . Parallel program schemata. J. Comput. & Syst. Sci. , 147 - 195
    3. 3)
      • F.G. Heath . Research in progress. Comput. Aided Des. , 3 , 171 - 173
    4. 4)
      • F.G. Heath , D. Bain . Simplified method for establishing determinacy in a directed-graph control structure. Electron. Lett. , 16 - 17
    5. 5)
      • Howard, B.V.: `The manipulation of simple computation schemata', RM/75/6, Research Memorandum, 1975.
    6. 6)
      • Howard, B.V.: `Asynchronous control circuits for directed graphs', RM/74/l, Research Memorandum, 1974.
    7. 7)
      • Bain, D.: `Systematic approach to developing determinate pipeline schemata', RM/75/2, Research Memorandum, 1975.
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