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Buffered stack memory organisation

Buffered stack memory organisation

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Slow unidirectional shift registers can be used to realise a large-size inexpensive stack. A simple configuration of such a shift-register stack will frequently force a processing unit needing access to it into an idle state. In the letter, a scheme using a small number of fast bidirectional shift registers appended to a unidirectional shift-register stack is suggested. This configuration makes the entire stack look, for most of the time, as if it were made of fast bidirectional shift registers. A design method is presented to determine the number of bits needed in the bidirectional shift register to meet given specifications.

References

    1. 1)
      • M.E. Hoff , S. Mazor . Operation and application of MOS shift registers. Comput. Des. , 57 - 62
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19750231
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