Improved binary multiplication system

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Improved binary multiplication system

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An improved binary multiplication system is proposed employing a combination of lookup multiplication tables and addition units. The system is capable of operation at high speeds with complete accuracy.

Inspec keywords: digital arithmetic; multiplying circuits; digital circuits

Other keywords: multiplying circuits; binary multiplication system; digital circuits

Subjects: Digital arithmetic methods

References

    1. 1)
      • `Digital multiplying arrangement', 50508, 1972, British Patent Application.
    2. 2)
      • R. De Mori . Suggestion for an i.c. fast parallel multiplier. Electron. Lett. , 50 - 51
    3. 3)
      • L. Dadda , D. Ferrari . Digital multipliers: a unified approach. Alta frequenza , 1079 - 1086
    4. 4)
      • Monteath, G.D., Devereux, V.G.: `Digital methods in television', EL-12, 1967/55, BBC research department report, .
    5. 5)
      • Chambers, J.P.: `Digital multiplication and linear interpolation', 1972/35, BBC research department report, .
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